tp5322 rev. 3 september 14, 2004 1 initial release p-channel enhancement-mode vertical dmos fet features low threshold, -2.4v max. high input impedance low input capacitance, 110pfmax. fast switching speeds low on resistance free from secondary breakdown low input and output leakage complementary n- and p-channel devices application logic level interfaces-ideal for ttl and cmos battery operated systems photo voltaic devices analog switches general purpose line drivers telecom switches absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55c to +150c soldering temperature**** 300c ****distance of 1.6mm from case for 10 seconds. general description these low threshold enhancement-mode (normally-off) transistors utilize an advanced ve rtical dmos structure and supertex's well-proven silicon-gate manufacturi ng process. this combination produces devices with the power handling capabilities of bipolar transis tors and with the high input impedance and positive tem perature coefficient inherent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. supertex's vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high br eakdown voltage, high input impedance, low input c apacitance, and fast sw itching speeds are desired. package options ordering information order number / package to-243aa** to-236ab*** bv dss / bv dgs r ds(on) (max) v gs(th) (max) i d(on) (min) tp5322n8 tp5322k1 -220v 12 ? -2.4v -0.7a tp5322n8-g* TP5322K1-G* -220v 12 ? -2.4v -0.7a **same as sot-89. product suppli ed on 2000 piece carrier tape reels. ***same as sot-23. products suppli ed on 3000 piece carrier tape reels. tp5322 a04200 5 * "green" certified package d s d g d s g to-236ab (sot-23)* to-243aa (sot-89)* product marking for sot-89 tp3c ? where ? =2-week alpha date code product marking for sot-23 p3c ? where ? =2-week alpha date code
tp5322 rev. 3 september 14, 2004 2 thermal characteristics package i d (continuous) i d (pulsed) power dissipation @ t a = 25c jc c/w ja c/w i dr * i drm to-243aa -0.26a -0.90a 1.6w 15 78** -0.26a -0.9a to-236ab -0.12a -0.70a 0.36w 200 350 -0.12a -0.7a *i d (continous) is limited by max rated tj. **mounted on fr4 board, 25mm x 25mm x 1.57mm. signifi cant pd increase possible on ceramic substate. electrical characteristics (@25c unless otherwise specified) symbol parameter min typ max units conditions bv dss drain-to-source breakdown voltage -220 v v gs = 0v, i d = -2ma v gs(th) gate threshold voltage -1.0 -2.4 v v gs = v ds , i d = -1ma ? v gs(th) change in v gs(th) with temperature 4.5 mv/c v gs = v ds , i d = -1ma i gss gate body leakage -100 na v gs = 20v, v ds = 0v -10 a v gs = 0v, v ds = max rating i dss zero gate voltage drain current -1.0 ma v gs = 0v, v ds = 0.8 max rating, t a = 125c i d(on) on-state drain current -0.7 -0.95 a v gs = -10v, v ds = -25v 10 15 v gs = -4.5v, i d = -100ma r ds(on) static drain-to-source on-state resistance 8.0 12 ? v gs = -10v, i d = -200ma ? r ds(on) change in r ds(on) with temperature 1.7 %/c v gs = -10v, i d = -200ma g fs forward transconductance 100 250 mmho v ds = -25v, i d = -200ma c iss input capacitance 110 c oss common source output capacitance 45 c rss reverse transfer capacitance 20 pf v gs = 0v, v ds = -25v f = 1mhz t d(on) turn-on delay time 10 t r rise time 15 t d(off) turn-off delay time 20 t f fall time 15 ns v dd = -25v, i d = -0.7a r gen = 25 ? v sd diode forward voltage drop -1.8 v v gs = 0v, i sd = -0.5a t rr reverse recovery time 300 ns v gs = 0v, i sd = -0.5a notes: 1) all dc parameters 100% tested at 25c unless otherwise stated. (pulsed test: 300s pulse at 2% duty cycle.) 2) all ac parameters sample tested. switching waveforms and test circuit r gen input puls e ge ne r ato r v dd r l d.u.t output 0v -10v 0v v dd t d(off) input outp ut t r t f t d(on) t (on) t (off) doc.# dsfp-tp5322 a042005
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